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Silicon Labs /EFR32BG24A020F1024IM40 /CMU_S /TRACECLKCTRL

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Interpret as TRACECLKCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)CLKSEL 0 (DIV1)PRESC

PRESC=DIV1, CLKSEL=DISABLE

Description

No Description

Fields

CLKSEL

Clock Select

0 (DISABLE): TRACE clock is disable

1 (SYSCLK): SYSCLK is driving TRACE

2 (HFRCOEM23): HFRCOEM23 is driving TRACE

3 (HFRCODPLLRT): HFRCODPLLRT is driving TRACE
PRESC

TRACECLK Prescaler

0 (DIV1): TRACECLK is SYSCLK divided by 1

1 (DIV2): TRACECLK is SYSCLK divided by 2

2 (DIV3): TRACECLK is SYSCLK divided by 3

3 (DIV4): TRACECLK is SYSCLK divided by 4

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data